1. Technical Field
The present invention relates to a clock generating apparatus, a test apparatus, and a clock generating method.
2. Related Art
A known device (for example, DDR-SDRAM) outputs in parallel a data signal and a clock signal representing when to obtain the data signal. When designed to test such a device, a test apparatus utilizes multi-strobe capability to test the relation between the phase of the data signal and the phase of the clock signal.    Patent Document 1: Japanese Patent Application Publication No. 2003-315428    Patent Document 2: Japanese Patent Application Publication No. 2004-127455
To test a device configured to output in parallel a data signal and a clock signal, a test apparatus needs to adjust, in advance of the test, multiple strobes so that the strobes are generated at appropriate timings. The test apparatus, however, has difficulties in performing the adjustment automatically.
Another known device outputs a signal obtained by superimposing a clock component onto a data signal (for example, a device compatible with the serial ATA I/F standard). To test such a device, a test apparatus needs to recover the clock from the data signal output from the device. The test apparatus, however, cannot test such a device since it cannot automatically recover the clock from the data signal despite its multi-strobe capability.
In the future, a device can be proposed that outputs in parallel a data signal and a clock signal between which the relation in phase is indeterminate. To test such a device, a test apparatus needs to recover, in advance of the test, the clock from the data and clock signals output from the device. When testing such a device using the multi-strobe capability, however, the test apparatus is required to perform complicated clock pull-in process.